Technology
Difference between EEPROM and Flash memory.
- Flash memory is a non volatile storage memory which is electrically erasable and
programmable one.
- Flash memory is a special type of EEPROM.
- Flash memory can be erased and programmed in large blocks where as in EEPROM it
is in small blocks.
- Erase cycles are slow in EEPROM, this is advantages for flash memory for speed up
operations.
- Flash memory takes less power compared to the EEPROM.
- EEPROMS are generally used to store configuration information and booting
information.
- Flash memories are used in USB, memory cards etc.
Explain about I2C protocol. Is it possible to have more number of masters in the same
I2C lines.
- I2C "Inter Integrated Circuit" is a low level communication protocol used between low
speed devices.
- It is a two wire interface one line for Clock and other is for data line.
- I2C is simplex communication protoocol.
- I2C follows Master - Slave Communication protocol.
- I²C bus is a multi-master bus, which means more than one device capable of initiating
a data transfer can be connected to it. Master provides theClock to the slave devices.
- In a 8-bit address line first bit is used to indicate start bit with remaining 7-bits it can
able connect 2^7 devices.
- The communication between ?Master and Slave is as follows
1. Master waits until it sees no activity on the I2C bus. The SDA and SCL lines are
both high. The bus is 'free'.
2. The Master MCU issues a start condition, telling that "its mine - I have started
to use the bus". This condition informs all the slave devices to listen on the serial data
line for instructions/data.
3. Provide on the SCL line a clock signal. It will be used by all the ICs as the
reference time at which each bit of data on the SDA line will be correct (valid) and can be
used. The data on the data line must be valid at the time the clock line switches
from 'low' to 'high' voltage.
4. The Master MCU sends the unique binary address of the target device it wants
to access.
5. Master MCU puts a one-bit message (called read/write flag) on the bus telling
whether it wants to SEND or RECEIVE data from the other chip. This read/write flag is an
indication to the slave node whether the access is a read or a write operation.
6. The slave node ICs will then compare the received address with its own
address. The Slave device with the matching address responds back with an
acknowledgement signal. If the address doesn't match, they simply wait until the bus is
released by the stop condition.
7. Once the master MCU receives the acknowledgement signal, it starts
transmitting or receiving and the data communication proceeds between the Master and
the Slave on the data bus. Both the master and slave can receive or transmit data
depending on whether the communication is a read or write. The transmitter sends 8-bits
of data to the receiver, which replies with a 1-bit acknowledgement. And the action of
data transfer continues.
8. When the communication is complete, the master issues a stop condition
indicating that everything is done. This action free ups the bus. The stop signal is just
one bit of information transferred by a special 'wiggling' of the SDA/SCL wires of the bus.
Explain abot SPI protocol. How slave able to know it is write operation or read operation.
- SPI serial peripheral interface is three wire communication protocol in this one line for
Clock, two wires for MISO & MOSI, one optional one for Chip Select(CS).
- It is a Master-Slave communication protocol.
- SPI operates at full duplex (means, signals carrying data can go in both directions
simultaneously).
- SPI can have more number of Master or more number of Slaves. Master initiates the
communication. If more number of Slave are present GPIO pins are used for CS.
- Gives higher throughput than I2C.
1. The communication is initiated by the master all the time. The master
first configures the clock, using a frequency, which is less than or equal to the maximum
frequency that the slave device supports. The master then select the desired slave for
communication by pulling the chip select (SS) line of that particular slave-peripheral
to "low" state.
2. A full duplex data transmission can occur during each clock cycle.
That means the master sends a bit on the MOSI line; the slave reads it from that same
line and the slave sends a bit on the MISO line; the master reads it from that same line.
3. Data transfer is organized by using Shift register with some given
word size such as 8- bits (remember, its not limited to 8-bits), in both master and slave.
They are connected in a ring. While master shifts register value out through MOSI line,
the slave shifts data in to its shift register.
